Samsung Fab will be the first semiconductor manufacturer to use a similar all-gate field effect transistor (GAAFET) structure in the upcoming 3 nm process. Although the node is not yet ready, at the IEEE International Solid-State Circuits Conference (ISSCC), Samsung fab engineers shared some details about the upcoming 3 nm GAE MBCFET (multi-bridge channel FET) fabrication technology.
According to the presentation, there are two types of GAAFETs: the typical GAAFET, which is called a nanowire with “thin” fins. And the MBCFET, which is called a nanosheet with “thick” fins. In both cases, the gate material surrounds the channel area on all sides. The actual implementation of nanowires and nanosheets depends heavily on the design, so in general, many industry observers use the term GAAFET to describe both. But previously they were known as surrounding-gate transistors (SGT). It is worth noting that MBCFET is a trademark of Samsung.
The GAAFET was first demonstrated worldwide in 1988, so the key advantages of the technology are well known. The structure of this transistor allows designers to precisely tune it by adjusting the width of the transistor channel (also called effective width or Weff) to achieve high performance or low power consumption. Wider sheets (sheets) allow for higher performance at higher power, while thinner/narrower sheets allow for lower power consumption and performance. In order to do something similar with FinFETs, engineers must use additional fins to improve performance. But in this case, the “width” of the transistor channel can only be doubled or tripled, which is not very accurate and sometimes very inefficient. In addition, since different transistors can be used for different purposes, the density of transistors can be increased by adjusting the GAAFET.
(Image source: Samsung)
(Image source: Samsung)
Back in 2019, Samsung introduced version 0.1 of its 3GAE process design kit that included four different nanosheet widths to provide some flexibility for early adopters, although it is unclear if the company has increased the width to provide additional flexibility. But Samsung says that overall, its 3GAE node will enable a 30 percent performance improvement (at the same power and complexity), a 50 percent power reduction (at the same clock and complexity), and an 80 percent increase in transistor density (including a mix of logic and SRAM transistors) compared to 7LPP technology.
(Image credit: Samsung)
Samsung’s 3GAE (its first generation of MBCFET technology) will be available in 2022. Although Samsung has not yet disclosed all its features. However, the company discussed at ISSCC how it will use the new transistors to improve SRAM performance and scalability.
In recent years, SRAM scalability has lagged behind logic scalability. Meanwhile, modern on-chip systems use SRAM loads for a variety of caches, so improving its scalability is a critical task.
(Image source: Samsung)
According to EE Times Asia, the Samsung foundry introduced its 256Mb MBCFET SRAM chip, which measures 56mm2 , at ISSCC. This means that although the company has not yet launched its first 3GAE logic chip, it is clear that the technology is suitable for SRAM.
SRAM is a six-transistor memory cell: two transfer gates, two pull-ups and two pull-downs. In a FinFET design, the SRAM cell will use the same transistors with the same channel width. With the MBCFET, Samsung can adjust the channel width, so two options are proposed: in one case, Samsung will use transistors with wider channels for the pass gates and pull-down circuits, while in the other case, Samsung will use transistors with wider channels for the pass gates and transistors.
As for the narrower pull-down channels. Samsung, via IEEE Spectrum, says that by using transistors with wider channels for the transfer gate and transistors with narrower channels for the pull-up, Samsung managed to reduce the write voltage by 230 mV compared to a conventional SRAM cell .
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